Traditionally, multi video channel television display screens are equipped with dual channel video processing chips which enable a user to view one or more channels simultaneously on various portions of the display screen. This form of displaying a picture within a picture is commonly referred to as picture-in-picture or PIP. FIG. 1A is an example of displaying two channels on various portions of the display screen having an aspect ratio of 4:3. A screen 100A displays a first channel 112 on the majority portion of the screen simultaneously with a second channel 122 that is displayed on a substantially smaller portion of the screen. FIG. 1B is an example of a display having a first channel and a second channel with substantially the same aspect ratio on different portions of the screen and will be described in more detail below.
A typical television system for generating PIP display 100A is shown in FIG. 2. Television display system 200 includes, television broadcast signals 202, a hybrid TV tuner 210, baseband inputs 280, a demodulator 220, an MPEG Codec 230, an off-chip storage 240, an off-chip memory 300, video processor 250, and an external component 270 (e.g., a display). Hybrid TV tuner 210 can tune to one or more television channels provided by television broadcast signals 202. Hybrid TV tuner 210 may provide digital television signals to demodulator 220 and analog video signal components (e.g., Composite Video Baseband Signals (CVBS)) to video processor 250. Additionally, baseband inputs 280 may receive various television signals (e.g., CVBS, S-Video, Component, etc.) and provide them to video processor 250. Other external digital or analog signals (e.g., DVI or High Definition (HD)) may also be provided to video processor 250.
The video is demodulated by demodulator 220 and is then decompressed by MPEG Codec 230. Some operations required by MPEG Codec 230 may use off-chip storage 240 to store data. The digital signal(s) are then processed by video processor 250, which can be a dual channel processing chip, in order to generate the proper signals 260 for display on external component 270. Video processor 250 may use off-chip memory 300 to perform memory intensive video processing operations such as noise reducing and de-interlacing; 3D YC seperation and frame rate conversion (FRC).
In these PIP applications, it is generally perceived that first channel 112 is more important than second channel 122. Typical dual channel processing chips that are used to generate PIP place more quality emphasis on the first channel video pipe, which generates the large display of first channel 112. The second channel video pipe, which generates the smaller display of second channel 122 is of lesser quality in order to reduce costs. For example, 3-D video processing operations, such as de-interlacing, noise reduction, and video decoding, may be implemented on the first channel video pipe while implementing only 2-D video processing operations on the second channel video pipe. 3-D video processing operations refer to operations that process video in the spatial and temporal domains, often buffering one or more frames of video used in the processing operations. In contrast, 2-D video processing operations only process video in the spatial domains, operating only on the current frame of video.
With the advent of wide display screens having an aspect ratio of 16:9, displaying two channels having the same size or an aspect ratio of 4:3 on the same screen has become increasingly higher in demand. This form of application is commonly referred to as picture-and-picture (PAP). In FIG. 1B screen 100B displays a first channel 110 and a second channel 120 having substantially the same aspect ratio is displayed on a second portion of the screen. In these applications the first channel should be generated with similar quality as the second channel.
An implementation of 3-D video processing on both the first and second video channel pipes is therefore needed to produce two high-quality video images. Performing 3-D video processing to produce the desired display generally requires memory intensive operations that have to be performed within a time frame suitable to display the images without loss in quality or integrity. The memory operations increase proportionally with the number of channels that require 3-D video processing. Typical dual video processing chips lack ability to process two video signals with high-quality and are therefore becoming obsolete with the increase in demand to display two channels having high video quality.
One reason that typical dual video processing chips lack in the ability to process multiple high-quality video signals, is the large amount of data bandwidth required between the video processor and the off-chip memory. Traditionally, a portion of the video processing chip pipeline includes a noise reducer and de-interlacer each requiring high data bandwidth with the off-chip memory.
In particular, the noise reducer works primarily by comparing one field to the next field and removing portions of the field that are not the same in each field. For this reason, the noise reducer requires storage of at least two fields for comparison with a current field. The de-interlacer reads the two fields that were stored and combines them, thereby reversing the operations of the interlacer.
FIG. 3 illustrates the off-chip memory access operations of the noise reducer and de-interlacer of a typical video processor. A portion of the video processing pipeline includes a noise reducer 330, a de-interlacer 340, and off-chip memory 300, which contains at least four field buffer sections 310, 311, 312, and 313.
During a first field interval, noise reducer 330 reads a field buffer section 310 compares it to a video signal 320, produces a new field with reduced noise and writes this field output 322 to two field buffer sections 311 and 312. The contents that were previously stored in field buffer sections 311 and 312 are copied over to field buffer sections 310 and 313, respectively. Thus, at the end of the field interval, field output 322 of noise reducer 330 is stored in field buffer sections 311 and 312 and the fields previously stored in field buffer sections 311 and 312 are now in field buffer sections 310 and 313, respectively.
During the following field interval, field buffer section 312 containing the field output from noise reducer 330 from the previous field interval is read by de-interlacer 340, field buffer section 313 containing the field output from noise reducer 330 from the field interval previous to this field interval that was stored in field buffer section 312 is read by de-interlacer 340. Field output 322 of noise reducer 330 of the current field interval is also read by de-interlacer 340. De-interlacer 340 processes these field segments and combines them to provide a de-interlaced output 342 to the next module in the video pipeline.
The exemplary aforementioned video pipeline portions perform these operations for a single channel and its operations would be multiplied for each additional channel. Therefore, since memory access bandwidth increases proportionally with the amount of data that has to be written/read in the same interval, performing noise reduction and de-interlacing on multiple channels would increase the data bandwidth in the same manner. The incredible bandwidth demand of the above video processing operations limit the ability to perform these operations simultaneously.
Therefore, it would be desirable to have systems and methods for reducing memory access bandwidth in various sections of one or more video pipeline stages of one or more channels in order to produce a display having multiple high-quality video channel streams.